1. Field of the Invention
The present invention relates generally to a system for enabling a test mode in a device, and, more particularly, to a method and apparatus for enabling a program verify mode in an erasable programmable read-only memory (EPROM).
2. Description of the Related Art
The need for a special test mode in a semiconductor device has manifested itself in a variety of different ways. In particular, a memory device, such as an EPROM, has a program verify mode to determine whether a program operation has been successfully performed. Those of ordinary skill in the art will recognize that an apparatus known as an EPROM programmer may be used to perform the programming, and verify operations. The EPROM programmer conventionally applies a selected address to the EPROM, further applies the user-specified data to be written at that address, and then, to perform the actual programming operation, asserts predetermined control signals, and applies a programming "pulse". The programmed EPROM bit is then read (i.e., "verified") to ensure that it was programmed correctly. Were the bit found to be incorrectly programmed, then the EPROM programming machine may be controlled in some circumstances to apply a second (and further) programming pulse to the same address in an effort to program it correctly. This "multi-pulse" programming is often required due either to poor high voltage levels generated by the EPROM programmer, adverse noise conditions, or a weak bit in the EPROM array. In the case of a weak bit (a common fault), the ability to apply multiple "pulses" is very useful, since it allows greater yield and reliability, either when sorting such memory devices after fabrication, or when put into the customer's hands (e.g., when programmed by an EPROM programmer apparatus).
A particular type of verify mode is often provided on EPROMs which adds some margin to the standard read mode. In particular, when an address is read using this special verify mode, it must be over-programmed (i.e., have extra margin) or else the read operation will fail. Thus, this special verify mode ensures that some margin always exists on programmed memory cells. Multi-pulse programming and the above-mentioned special verify mode thus cooperate to improve both the yield and the reliability of the part.
Further, conventional EPROMs generally have control terminals or pins available for a programming voltage (V.sub.pp), output enable signal (OE/OE), a programming signal (PGM/PGM) and a chip enable signal (CE/CE) . One approach taken in providing the above-mentioned special verify mode is asynchronous in nature, and requires a dedicated control pin for implementation. In particular, such an approach requires that a supervoltage (i.e., a higher-than-V.sub.cc, voltage used for programming), applied to the V.sub.pp pin during programming, be maintained while taking the output enable pin low to enter the special verify mode. For a standard read (verify operation), the supervoltage would be otherwise removed from the V.sub.pp pin. Thus, with this approach, a dedicated pin (namely, V.sub.pp) provides the means for distinguishing between a normal or standard read, and the special verify read mode. This approach is satisfactory as long as there are available pins so that the relevant control terminals may be properly asserted.
However, the trend in semiconductor devices has been to reduce the number of pins or terminals per package. In particular, one industry standard pin configuration (JEDEC) for an EPROM is a 28-pin package. This package is pin limited with respect to control signals. In particular, this standard specifies that one pin shall be for V.sub.pp /OE, an another pin will be for CE/PGM. This particular industry standard further specifies that no pins other than control pins may be used to decode the special verify mode (e.g., an address pin may not be used to decode this mode).
A problem thus arises when attempting to implement the above-mentioned special verify mode in such a pin-limited package. In particular, after a programming operation where V.sub.pp is at supervoltage, the verify operation requires that the output enable (OE) be taken low in order to read the programmed bit. Since the output enable (OE) and the programming voltage V.sub.pp are implemented on the same pin in the JEDEC EPROM standard package, and (OE) must be taken low to enable the outputs for the read operation, the conventional manner of allowing V.sub.pp to remain at supervoltage to decode the special verify read mode is not possible. Since the conventional asynchronous decoding techniques are unavailable in the above-described or similarly pin-limited packages, such a device is unable to distinguish the special verify mode from a standard read mode. Without the special verify mode (i.e., having the extra read margin) the advantages of improved yield and reliability at sort and in customer's hands may not be available in such a device.
Thus, there is a need to provide an improved system for enabling a test mode in a semiconductor device that reduces or eliminates one or more of the problems as described above.